How Far Has China's Chips Caught Up? Ascend, SMIC, and the Thickness of the Silicon Shield

Start with the side that keeps people up at night. Stop comforting yourself with "China's yields are low" — that was the 2023 script.

China's leading foundry, SMIC, without any EUV lithography machine, has forced its way to a process equivalent to 7 nanometers using older DUV (deep ultraviolet) lithography and multiple exposures. This route is expensive and difficult, but it has genuinely worked. Third-party estimates put SMIC's advanced-node (7nm and below) monthly capacity at about 45,000 wafers by the end of 2025, rising to about 60,000 in 2026 and as high as 80,000 by 2027 ^[3][4].

Even more striking is the yield. Huawei's Ascend 910C — the AI chip pitched against Nvidia — once had a yield low enough to make people shake their heads, but in 2025 it was reportedly pulled up to close to 40%, turning the entire Ascend line profitable for the first time ^[5]. 40% is still far below the industry's mature 60% standard, but "able to make money" means it has gone from "a political statement in a lab" to "a business that actually runs commercially." Huawei's 2026 target is to push Ascend 910C's annual output to about 600,000 units (a target figure), roughly double the year before ^[4].

The strategy has also changed. China has shifted from its earlier years of "fighting head-on for the most cutting-edge node" to "ramping up existing capability and feeding it to AI chips first." It is no longer fixated on producing the single strongest chip in the world — it is first pursuing "good enough, and enough of it." For an economy under blockade, this pragmatic pivot is more dangerous than any single technological breakthrough.

But flip the same set of numbers over, and there are three walls — very hard, very difficult to tear down in the short term.

The first wall is yield and cost. Using DUV for 7nm is like using an ordinary brush to paint fine, detailed brushwork — it can be done, but the cost, time, and scrap rate per wafer are all far higher than at TSMC, which uses EUV. A 40% yield means throwing away six out of every ten chips printed, an enormous waste in peacetime that only holds up under the logic of a "cost-no-object national project."

The second wall is HBM (high-bandwidth memory). This was once the most fatal ceiling on China's AI computing power. For an AI chip to run fast, it needs large amounts of HBM stacked like a sandwich next to the compute core; and high-end HBM capacity is almost monopolized by South Korea's Samsung, SK Hynix, and Micron, and was placed under U.S. controls on China at the end of 2024. Without HBM, even the strongest compute core is "an engine with no fuel line."

The third wall is the equipment ecosystem. Semiconductor self-sufficiency was never something that "being able to make chips" alone could achieve — it requires domestic memory, domestic equipment, and domestic EDA design software, with the entire ecosystem falling into place together ^[4]. If any one link runs short, the whole chain seizes up. Huawei previously even had to "route around" this by having TSMC fab about 2 million AI chip dies for it, which shows exactly how domestic capacity still can't support its ambitions ^[4].

Measure the spear and the shield together: what Nvidia makes at TSMC is N2 (2-nanometer) class; China's mainstream production is still enhanced 7nm. The single-chip gap at the cutting edge is still about two generations ^[8]. International think tanks such as the Council on Foreign Relations (CFR) argue on this basis that Huawei cannot catch Nvidia in the short term, and export controls should continue ^[8].

So if the story ended here, the conclusion would be reassuring: "the silicon shield is still thick, go back to sleep."

But 2026's real plot only begins from here.

This is the lesson Taiwan most often overlooks, and most needs to catch up on: when you can't win chip-for-chip, you can change the question you're competing on.

Huawei's calculation goes like this: a single Ascend can't beat a single Nvidia chip? Fine — make up for it with "more chips, wired into a bigger whole." It strings tens of thousands of weaker cards together into one giant "superpod" (SuperPoD) using its own self-developed high-speed interconnect technology. The already-deployed CloudMatrix 384 superpod binds 384 cards into a single machine; and on the roadmap, the Atlas 960 SuperPoD aims to push the card count all the way to 15,488 by 2027 (a target figure) ^[8].

The essence of this move is: AI training is a contest over "the total compute of the whole cluster," not "the peak performance of a single chip." Like a war, the winner isn't necessarily the side with the strongest individual soldier — it's the side that can coordinate the most troops effectively. China's individual chip may be two generations behind, expensive, and power-hungry, but as long as it can wire enough cards together effectively, it has a chance to close in on — or even locally surpass — total compute at the "rack level" and "data-center level."

This is exactly why looking only at "how many nanometers behind the process is" leads to serious misjudgment. China is using "system-level scale" to make up for "chip-level generational gaps" — using engineering and organizational capability to route around a physical wall it cannot climb over for now.

We said in an earlier piece: don't get hung up on "has China caught up or not" — watch two variables that will directly rewrite the equation: HBM and EUV.

From late 2025 into 2026, these two alarms went off almost simultaneously.

First, the HBM wall has been routed around through "self-development." Rather than foolishly waiting for someone else to lift the ban, Huawei announced that its 950 series will switch to HBM it developed itself (codenamed HiBL and HiZQ), claiming bandwidth of up to 1.6 TB/s, co-developed with Chinese memory maker CXMT ^[7]. This is a classic Chinese response: if you ban me from buying, I'll build it myself. Of course, the wall isn't that easy to get around — industry outlet DigiTimes has reported that CXMT's HBM3 mass-production timeline is actually "slipping," and real 12-layer stacked mass production may not catch up to South Korea until 2027 ^[6]. So this wall is "under attack, but not yet down."

Second, the first crack has appeared in the EUV wall. In December 2025, a highly secretive research facility in Shenzhen reportedly validated a domestic EUV lithography prototype — the first time a Chinese-built system had stably produced a 13.5-nanometer EUV beam. It follows a different technical path from ASML (LDP, laser-produced plasma), with lower power (about 100–150W, versus ASML's 250W-plus), but it is a "zero to one" step. This "whole-of-nation" effort is led by Huawei and Shenzhen SiCarrier, aiming for 2028 mass production for AI-chip supply ^[10]. A separate route at Tsinghua University, SSMB (steady-state microbunching), even aims to skip ASML's current generation altogether ^[11].

But here we have to honestly hit the brakes. The American think tank CSIS's attitude toward this kind of news is a cool-headed question: "Is this a breakthrough, or a boast?" (Breakthroughs or Boasts?) ^[9]. A machine that has "validated a prototype" is still a very long way from "stable, high-yield, large-scale mass production"; China has no shortage of past "major breakthroughs" that later turned out to lead nowhere. So the correct reading is: the crack has appeared, but the wall hasn't fallen — this is a signal to watch, not a settled fact (confidence: medium).

If everything above is "the rival raising itself up," then the most underrated change of 2026 is "America lowering its own wall."

Over the past few years, U.S. chip controls on China had tightened steadily: two rounds of export controls in 2022 and 2023, and HBM and advanced packaging brought under controls at the end of 2024 ^[13]. The higher this "wall," the more it hurts China, and the more valuable TSMC's generation gap becomes — the thicker the silicon shield.

But once the Trump administration took office, the direction turned. Nvidia's H20 chip, designed specifically for China, was at one point required in April 2025 to apply for a license case by case, effectively blocking it; then in July, policy reversed sharply and shipments were allowed again. More critically, in December 2025 Washington announced it would review and allow the stronger H200 to be exported to China on a case-by-case basis; by May 2026, Nvidia's H200 and AMD's MI308 could already be sold into China ^[1][2]. Nvidia even custom-built the Blackwell-generation B30A for China, said to reach about 80% of the standard version's performance.

This is a subtle and dangerous signal for the silicon shield. When America, for commercial gain, is willing to sell near-top-tier chips back to China, it is effectively doing two things at once: first, giving China's AI industry live ammunition to train with and close the gap; second, making the silicon shield's core proposition — that "the most cutting-edge chips made in Taiwan are irreplaceable" — no longer quite so absolute. How thick the silicon shield is has never depended only on how fast China catches up — it also depends on how high Washington is willing to build the wall. And that wall is now being lowered from the inside.

Putting the three faces together — China ramping up volume, changing the question, attacking the wall; America loosening its grip — the most honest description is:

The "most cutting-edge" slice of the silicon shield is still very thick; but the "good enough" slice is getting thinner.

On the bright side, Taiwan isn't just holding its own at the real high ground — it's pulling further ahead. TSMC entered volume production at 2 nanometers (N2) in the fourth quarter of 2025, the only fab in the world able to supply this generation at scale; A16 (with backside power delivery) is scheduled for the second half of 2026 ^[12]. For CoWoS, the advanced packaging most critical to AI chips, TSMC's capacity is surging from about 35,000 wafers a month at the end of 2024 toward about 130,000 by the end of 2026, and it is already booked solid by customers such as Nvidia ^[12]. The most cutting-edge production lines are confirmed to stay in Taiwan through the end of this decade ^[10]. This is the silicon shield's hardest slice.

But on the dark side, China's "good enough, plentiful, and cheap" self-sufficiency will eat away at Taiwan's market from below, layer by layer: mature-process orders, China's own domestic market, price-sensitive low-and-mid-range applications. It may never catch up at the cutting edge, but it doesn't need to — it only needs to reach scale at the "good enough" level to shift the industry's entire center of gravity.

So both red teams are right, and both must be heard together: the Eastern Eye says don't comfort yourself with low yields — Ascend is shipping, the roadmap runs to 2028, and system-level scale is closing in; that's real. The Western Eye says "good enough" is not "equal" — self-developed HBM will slip, domestic EUV may be a boast, the single chip is still two generations behind, and the generation gap remains. The sentence truly worth remembering is: the silicon shield's generation gap is indeed still there, but it isn't eternal — and its lifespan is written half in the rival's bottlenecks, and half in Washington's choices.

For the state: manage the silicon shield as a "variable that can change," not a "wall that's always there." Set up three warning lights to monitor regularly: (1) the real mass-production progress of Huawei's self-developed HBM and CXMT; (2) the milestones of domestic EUV moving from "prototype" to "mass production"; (3) how tight or loose U.S. controls are — this is the light most overlooked in the past, yet possibly the most critical. Export controls (continuing the discussion in "The Gate Changes Hands") need to be aimed precisely at the real bottlenecks — HBM, advanced equipment, EDA, CoWoS — rather than being applied indiscriminately and simply raising costs for Taiwan's own industry.

For the semiconductor industry: hold two moats — the most cutting-edge nodes (N2/A16) and advanced packaging (CoWoS/HBM integration, continuing the discussion in "Silicon Shield in Depth"). These are what China finds hardest to replicate in the short term, and where the silicon shield's value gets cashed in. At the same time, stay clear-eyed: China's "good enough" self-sufficiency will keep eroding Taiwanese firms' low-and-mid-range and domestic-market orders from the mature-process end — that ground can't be held, and there's no need to pretend it isn't happening.

For SMEs: mature processes (28nm and above) are the red ocean where China's capacity dumping will flood in fastest. Related design-service, packaging-and-testing, and equipment SMEs should move early toward specialty processes (automotive, sensing, power devices) and niche applications, avoiding head-on price wars — treating "technical uniqueness," not "capacity scale," as their protective charm.

Back to that roadmap from September 2025. Eric Xu's willingness to lay out a product three years out is not a bet that "my next chip beats Nvidia's" — he knows he can't win that bet in the short term. What he's betting on is: as long as I can, through volume, systems, self-development, and a whole-of-nation effort, make "good enough" big enough, the West's wall will eventually fail to hold.

And the homework Taiwan needs to do is not to anxiously ask "has he caught up yet" — it's to calmly watch three pieces that haven't settled into place yet: HBM, EUV, and the wall in Washington that could be lowered at any moment.

To measure how thick a shield is, you have to see how sharp the rival's spear has gotten. This spear of China's has a blade that is getting sharper, a shaft that hasn't yet been fully fitted — but the hand holding it is no longer hiding. The shield's lifespan is written in the rival's bottlenecks, and it is also written in an ally's choices — and Taiwan has to keep a close eye on both, itself.